Embodiments of the present invention relate to a semiconductor device layout and a method for forming the same, and more particularly to a layout of a decoupling capacitor of a semiconductor device, and a method for forming the same.
With the increasing degree of integration of semiconductor devices (for example, Dynamic Random Access Memory (DRAM)), the demand for higher storage capacity and higher operation speeds is rapidly increasing. Generally, the number of operation circuits is increasing in proportion to the increasing degree of integration of semiconductor devices. In integrated devices, high fluctuation noise may instantaneously occur in a power-supply voltage (VDD) and a ground voltage (VSS) during a read or write operation. In order to address the above-mentioned issues, a decoupling capacitor for filtering noise encountered between the power-supply voltage (VDD) and operation power such as the ground voltage (VSS) has been widely used in the semiconductor devices. The decoupling capacitor is typically arranged in an available space of a peripheral region.
The decoupling capacitor may reduce high-frequency noise, may further provide a power source for the semiconductor device, and may exclude inductance components generated when an external power source is coupled to the semiconductor device, thereby improving impedance from the viewpoint of the external power source.
In a semiconductor device, a decoupling capacitor is typically metal oxide semiconductor (MOS) capacitor having a larger capacitance in a small region. MOS capacitors are classified as NMOS capacitors and PMOS capacitors. Generally, NMOS capacitors have superior characteristics than PMOS capacitors, so that NMOS capacitors have been widely used.
A detailed description of an exemplary case in which an NMOS capacitor is used will hereinafter be described in detail. If a power-supply voltage (VDD) is applied to a gate terminal of the NMOS transistor, and a ground voltage (VSS) is commonly applied to a source terminal, a drain terminal, and a bulk terminal of the NMOS transistor, the NMOS transistor can be used as a capacitor. Theoretically, if a voltage level (Vgs) between the gate and the source is less than a threshold voltage (Vt), the NMOS transistor is not turned on, no current flows, and electric charges are stored in the NMOS transistor, so that the NMOS transistor can be used as a capacitor.
However, the above-mentioned decoupling capacitor may cause two parasitic resistance components. The two parasitic resistance components increase the number of power drops in proportion to a higher parasitic resistance, and thus deteriorate high-frequency operation characteristics. One of the parasitic resistance components is Equivalent Series Resistance (ESR). ESR is unique resistance of the decoupling capacitor, such that the ESR can change and adjust characteristics of the decoupling capacitor. The lower the ESR, the higher the operation characteristics of a high-frequency region. However, metal lines for applying the power-supply voltage (VDD) and the ground voltage (VSS) to the decoupling capacitor need to be formed, and a path resistance occurs in the metal lines. In addition, if the decoupling capacitor is coupled to the metal line, additional metal lines need to be arranged, resulting in an increased size.